Nanosheet devices can be viable device options instead of fin field-effect transistors (FinFETs). For example, nanowires or nanosheets can be used as the fin structure in a dual-gate, tri-gate or gate-all-around (GAA) FET device. Complementary metal-oxide semiconductor (CMOS) scaling can be enabled by the use of stacked nanowires and nanosheets, which offer superior electrostatics and higher current density per footprint area than FinFETs. Additionally, nanosheet devices are being pursued as a viable device option for the 5 nm node and beyond. Nanosheet formation relies on the selective removal of one semiconductor (e.g., silicon germanium (SiGe)) with respect to another (e.g., silicon (Si)) to form the nanosheet and GAA structures.
Work function metal (WFM) removal in nanosheet processing requires extensive over-etching to remove WFM layers between nanosheets. In connection with adjacent n-type and p-type nanosheet devices (e.g., nFETs and pFETs), a first type nanosheet device (e.g., n-type) is typically formed by etching the opposite type (e.g., p-type) WFM on the first type side and subsequently depositing the first type WFM to replace the removed opposite type WFM. However, when using conventional methods, the etching of the opposite type WFM on the first type side also damages and causes unwanted removal of part of the opposite type WFM on the opposite type side. As a result, conventional lateral etch processes undesirably limit the minimum distance between n-type and p-type nanosheet devices, and undesirably limit the width of nanosheets.
Due to increased device density and longer nanosheet widths being employed in many applications (e.g., static random-access memory (SRAM)), reduced distance between n-type and p-type nanosheet devices is required. Accordingly, there is a need for improved methods for WFM removal in nanosheet processing which allows for reduction of the distance and between n-type and p-type nanosheet devices and increased nanosheet width.